1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit provided with an internal power supply circuit such as a stepped-up power supply circuit or stepped-down power supply circuit.
2. Description of the Related Art
In semiconductor integrated circuits, a stepped-up voltage Vpp and/or a stepped-down voltage Vii are generated from an external power supply voltage Vdd for provision to the core circuit. In semiconductor memory devices, for example, a stepped-up voltage Vpp is used to drive a word line or the like, and a stepped-down voltage Vii is used as a power supply voltage in the memory core circuit and peripheral circuits. In order to generate the stepped-up voltage and stepped-down voltage, power supply circuits such as a stepped-up voltage generating circuit and a stepped-down voltage generating circuit are used.
A stepped-up voltage generating circuit includes a detector circuit and a pump circuit. When the detector circuit detects a drop of the stepped-up voltage, the pump circuit is activated in response, thereby raising the stepped-up voltage. FIG. 1 is a circuit diagram showing an example of the configuration of the detector circuit.
The detector circuit of FIG. 1 includes NMOS transistors 11 through 13, PMOS transistors 14 and 15, resistors 16 and 17, and an inverter 18. The resistors 16 and 17 together constitute a potential divider, which divides the stepped-up voltage Vpp. The NMOS transistors 11 through 13 and the PMOS transistors 14 and 15 together constitute a differential amplifier, which supplies to the inverter 18 a voltage responsive to a difference between a reference voltage Vref and the voltage made by dividing the stepped-up voltage Vpp. An output pump_on of the inverter 18 is supplied to the pump circuit. When the stepped-up voltage Vpp drops, the voltage obtained by dividing the stepped-up voltage Vpp becomes smaller than the reference voltage Vref, resulting in the input into the inverter 18 being LOW. As a result, the output pump_on becomes HIGH. In response, the pump circuit is activated to raise the stepped-up voltage Vpp.
FIG. 2 is a diagram showing changes in the stepped-up voltage Vpp. As shown in FIG. 2, the stepped-up voltage Vpp gradually drops due to leak currents in the core circuit during the standby mode of the semiconductor integrated circuit (i.e., the period indicated as pump-off in FIG. 2). When the stepped-up voltage Vpp drops to a predetermined level, the pump circuit is activated to boost the stepped-up voltage Vpp. When the stepped-up voltage Vpp rises to reach a predetermined level, the operation of the pump-circuit is suspended. In FIG. 2, the period during which the pump-circuit operates is indicated as pump-on. Through the operations described above, the stepped-up voltage Vpp is maintained at a constant potential.
In FIG. 1, a bias current Ib1 flowing through the NMOS transistor 11 is set to an amount corresponding to the operation speed required for the pump circuit active in operation (during the pump-on period shown in FIG. 2). If the bias current Ib1 is large, the operation speed of the differential amplifier shown in FIG. 1 is fast, thereby being able to detect a potential change in response to a rapid change in the stepped-up voltage Vpp. If the amount of the bias current Ib1 is insufficient, the operation speed during the pump-on period shown in FIG. 2 becomes insufficient. In this case, the potential detection is delayed, and the stepped-up voltage Vpp experiencing a rapid rise becomes an excessive voltage level exceeding a predetermined level. Because of this, the bias current Ib1 needs to be set to an amount corresponding to the operation speed required during the active operation of the pump circuit.
If the bias current Ib1 is set such as to fit with the operation period of the pump circuit, however, the current consumption of the bias current Ib1 during the pump-off period becomes a needless waste. That is because a large amount of the bias current Ib1 is used despite the fact that high response speed is not required during the pump-off period because changes in the stepped-up voltage Vpp are gradual.
In consideration of the above, there is a need for a configuration that can reduce current consumption in the stepped-up voltage generating circuit during the standby mode.
A needless current is also consumed in the stepped-down voltage generating circuit. FIG. 3 is a diagram showing a portion relating to the stepped-down voltage generating circuit. In FIG. 3, a power-down control circuit 21, a VGI generating circuit 22, NMOS transistors 23 and 24, and a power-down control pad 25 are illustrated. The NMOS transistor 24 serves as the circuit portion that generates the stepped-down voltage. The gate of the NMOS transistor 24 receives a predetermined gate voltage Vgi, with its drain node connected to a power supply voltage Vdd and its source node supplying an internal stepped-down potential Vii. When the stepped-down potential Vii drops due to current consumption in the core circuit, a difference between the gate potential Vgi and the source potential (the stepped-down potential Vii) widens, resulting in an increase in the current flowing through the NMOS transistor 24. In response, the stepped-down potential Vii rises. In this manner, the stepped-down potential Vii is controlled to be a constant potential defined by the gate potential Vgi.
In the configuration shown in FIG. 3, a signal from the exterior to the power-down control pad 25 is asserted during a power-down mode, resulting in an output signal PD of the power-down control circuit 21 becoming HIGH. The NMOS transistor 23 thus becomes conductive, turning the output of the VGI generating circuit 22 to LOW (i.e., a ground potential VSS), resulting in the NMOS transistor 24 being nonconductive. In this manner, the supply of the internal stepped-down voltage Vii to the core circuit is suspended during the power-down mode (for example, see Patent Document 1).
Depending on the type of the semiconductor integrated circuit, there may be a case in which it is desired to set the potential of the internal stepped-down voltage Vii to a voltage slightly higher than an ordinary voltage. In such a case, since there is a limit as to how high the gate voltage Vgi can be raised, it is a general practice to use a transistor having a small threshold voltage as the NMOS transistor 24. If a transistor having a small threshold voltage is used as the NMOS transistor 24, however, the NMOS transistor 24 will not be completely turned off even when the gate voltage Vgi becomes LOW in the power-down mode, resulting in a continuous flow of some electric current. Because of this, current consumption relatively increases during the power-down mode.
In consideration of the above, there is a need to provide a configuration that can reduce current consumption in the stepped-down voltage generating circuit during the power-down mode.
[Patent Document 1] Japanese Patent Application Publication No. 2002-373026.